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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. march 2008 rev 1 1/57 1 stw4510 2 step-down dc/dc converters / 5 ldo power management features 2 step-down converters ? vsdc1: 1 to 1.5 v with . 15 steps at 600 ma (i2c control available) . programmable start-up value (1.2v by default) ? vsdc2: 1.8 v at 600 ma for general purpose usage 5 low-drop output regulators for different uses ? vdig: 1.0v (100ma), 1.2v, 1.5v (250 ma) . can be supplied by vsdc2 to minimize the voltage drop . programmable start-up value (1.2v by default) ? vana1: 1.5, 1.8, 2.5, 2.8 v - 150 ma ? vana2: 1.8, 2.8, 3.0, 3.3 v - 150 ma ? vana3: 1.8, 2.8, 3.0, 3.3 v - 150 ma ? vmmc: 1.8, 2.5, 2.85, 3.0 v - 150ma miscellaneous ? vana(i) have programmable start-up output voltage and on or off (default) status ? 32 khz input used for state machine ? processor supply monitoring ? processor reset control ? control by serial i2c interface ? thermal shutdown applications any portable application ? mobile phones ? personal digital assistants (pda) ? portable media players description stw4510 is a 7-channel integrated power management device for application powered by one li-ion or li-polymer cell. stw4510 embeds 2 highly efficient step-down dc/dc converters and 5 ldo regulators. it has been designed to typically supply portable processor and its peripherals. thanks to the multiple output voltages, high current capability and programmable start-up value, it can easily adapt to various applications. tfbga84 6 mm x 6 mm x 1.2 mm 0.5 mm pitch tfbga49 4 mm x 4 mm x 1.2 mm 0.5 mm pitch www.st.com obsolete product(s) - obsolete product(s)
contents stw4510 2/57 contents 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 ball connections in tfbga84 6 mm x 6 mm package . . . . . . . . . . . . . . . . 7 2.2 ball connections in tfbga49 4 mm x 4 mm package . . . . . . . . . . . . . . . . 7 2.3 ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.1 signal description for the tfbga84 6 mm x 6 mm package . . . . . . . . . . 8 2.3.2 signal description for the tfbga49 4 mm x 4 mm package . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 digital control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 power off / vddok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.3 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.4 vsdc1_off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.5 power supplies at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.6 device reset by processor sw_resetn . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.7 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.8 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.9 it generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 power management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2 vsdc1 step-down dc/dc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.3 vsdc2 step down dc/dc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.4 vana1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.5 vana2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.6 vana3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.7 vdig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.8 vmmc power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.9 power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.10 thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 obsolete product(s) - obsolete product(s)
stw4510 contents 3/57 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.2 vref18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.3 vsdc1 dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.4 vsdc2 dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2.5 ldo regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2.6 power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3 digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1 cmos input/output static characteristics: i2c interface . . . . . . . . . . . . . 46 4.3.2 cmos input/output dynamic characteristics: i2c interface . . . . . . . . . . 47 4.3.3 cmos input/output static characteristics: vddio level . . . . . . . . . . . . . 47 4.3.4 cmos input static characteristics: vbat level . . . . . . . . . . . . . . . . . . . . 48 4.3.5 nmos input: pon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 test disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 guaranteed by design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 fully tested on package only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.1 tfbga 84 balls 6 mm x 6 mm x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2 tfbga 49 balls 4 mm x 4 mm x 1.2 mm . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 obsolete product(s) - obsolete product(s)
list of tables stw4510 4/57 list of tables table 1. stw4510 ball connections in tfbga84 6 mm x 6 mm x 1.2 mm package . . . . . . . . . . . . . 7 table 2. stw4510 ball connections in tfbga49 4 mm x 4 mm x 1.2 mm package . . . . . . . . . . . . . 7 table 5. low drop regulator output voltage programmable values. . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. vmmc low drop regulator output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. power supplies status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. thermal shutdown threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. stw4510 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. vref18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. vsdc1 dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. vsdc2 dc/dc step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. ldo regulators - vana 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. ldo regulator - vana(i) with i=2 or 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. ldo regulator - vdig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23. ldo regulator - vmmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. cmos input/output static characteristics: i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. cmos input/output dynamic characteristics: i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 27. vddio level: control i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. cmos input static characteristics: vbat level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. pon input static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 30. components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. list of 4.7 h coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. tfbga84 6 mm x 6 mm x 1.2 mm - 0.5mm ball pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 33. tfbga49 4 mm x 4 mm x 1.2 mm, 0.5mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 obsolete product(s) - obsolete product(s)
stw4510 list of figures 5/57 list of figures figure 1. stw4510 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. state machine: start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. switching from high power mode to sleep/vsdc1_off mode . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. vddok block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. control interface: i2c format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. control interface: i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. ldo on/off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. block diagram of biasing and references of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. stw4510 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. tfbga84 6 mm x 6 mm x 1.2 mm outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 11. tfbga49 4 mm x 4 mm x 1.2 mm outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 obsolete product(s) - obsolete product(s)
functional block diagram stw4510 6/57 1 functional block diagram figure 1. stw4510 block diagram vbat_vsdc2 vlx_vsdc2 gnd_vsdc2 vsdc2 vbat_vsdc1 vlx_vsdc1 gnd_vsdc1 vsdc1 clock switching and control internal oscillator clk32k_in vbat_osc gnd_osc vddio general control pon vddok res_pro pwren sw_reset gnd_io sda scl porn_vbat i2c interface soft_start vref bias vref_18 vbat_ana gnd_ana vsdc1 & vsdc2 monitoring thermal shutdown supply voltage selection vsdc1_sel<0> vsdc1_sel<1> vana3_sel>0> vana3_sel<1> vdig_sel<0> vdig_sel<1> vana1_sel<0> vana1_sel<1> vana2_sel<0> vana2_sel<1> vdig 1, 1.2, 1.5 v 100 or 250 ma vbat_dig gnd_vdig vdig vana1 1.5, 1.8, 2.5, 2.8 v 150 ma vbat_vana1_vana3 vana3 vana3 1.8, 2.8, 3.0, 3.3 v 150 ma gnd_vana1_vana3 vana1 vana2 150 ma vbat_vana2 gnd_vana2 vana2 vmmc 1.8, 2.85, 3.0 v 150 ma vbat_vmmc gnd_vmmc vmmc pon pwren pon pm00125 1. 8 , 2. 8 , 3 .0, 3 . 3 v obsolete product(s) - obsolete product(s)
stw4510 ball information 7/57 2 ball information the 6 mm x 6 mm package is useful for keeping all the selected value available for vana(i) (i=1 to 3), vdig and vsdc1. when using the 4 mm x 4 mm package, vdig is set to 1.2v, vsdc1 output voltage is controlled via i2c and vana(i) have only one selection bit available instead of 2. 2.1 ball connections in tfbga84 6 mm x 6 mm package 2.2 ball connections in tfbga49 4 mm x 4 mm package table 1. stw4510 ball connections in tfbga84 6 mm x 6 mm x 1.2 mm package 12345678910 a clk32k_in gnd_vsdc2 vlx_vsdc2 vbat_vsdc2 vsdc2 vdig vana1 vana3 vref_18 vsdc1 b ?reserved? ?reserved? gnd_vsdc2 vbat_vsdc2 gnd_ana vbat_vdig gnd_vana1 _vana3 ?reserved? ?reserved? gnd_vsdc1 c ?reserved? ?reserved? gnd_osc vlx_vsdc2 gnd_vdig vbat_ana vbat_vana1 _vana3 pon gnd_vsdc1 vlx_vsdc1 d vbat_osc ?reserved? ?reserved? vlx_vsdc1 vbat_vsdc1 vbat_vsdc1 e vsdc1_sel1 gnd_vana2 reserved f gnd_vana2 vbat_vana2 vana2 g gnd_io vana1_sel1 vddio h pwren sda vana3_sel1 vdig_sel1 reserved j vddok res_pro vbat_vmmc vdig_sel0 scl vana2_sel0 vana3_sel0 gnd_io reserved k sw_resetn vmmc vana1_sel0 vsdc1_sel0 vana2_sel1 reserved table 2. stw4510 ball connections in tfbga49 4 mm x 4 mm x 1.2 mm package 12 3 456 7 a gnd_vsdc2 vlx_vsdc2 vbat_vsdc2 gnd_ana vdig vbat_vdig vbat_vana1_ vana3 b gnd_vsdc2 vlx_vsdc2 vbat_vsdc2 vsdc2 vbat-ana vana1 vana3 c reserved reserved clk32k_in reserved pon gnd_vsdc1 gnd_vsdc1 d gnd_osc reserved reserved vref_18 vsdc1 vlx_vsdc1 vlx_vsdc1 e vbat_osc reserved vddok vana1_sel<0> reserved vbat_vsdc1 vbat_vsdc1 f res_pro sw_reset pwren sda vana2_ sel<0> vana3_ sel<0> vminus g vbat_mmc vmmc scl vana2 vbat_ana2 vddio vminus obsolete product(s) - obsolete product(s)
ball information stw4510 8/57 2.3 ball functions stw4510 includes the following ball types vddd/vdda: digital/analog power supply vssd/vssa: digital/analog ground supply do/di/dio: digital output / digital input / digital input-output doz: digital output with high impedance capability ao/ai/aio: analog output / analog input / analog input-output g: to be connected to ground o: to be left open 2.3.1 signal description for the tfbga84 6 mm x 6 mm package table 3. stw4510 ball description for the 6 mm x 6 mm package ball ball name ball type description general supply balls d1 vbat_osc vddd battery supply for digital/oscillator c3 gnd_osc vssd internal ground oscillator c6 vbat_ana vdda analog part battery supply b5 gnd_ana vssa analog ground a9 vref_18 ao internal reference g10 vddio vddd io digital supply g8, j9 gnd_io vssd io ground digital control balls c8 pon di (nmos) pull down 1.5m power-on and reset k4 sw_resetn di vddio voltage pull up 1.5m software reset, reset all application, when sw_resetn = 0 j2 vddok do vddio voltage supply monitoring for processor. interruption for high temperature warning j3 res_pro do vddio voltage reset for processor h6 pwren di vddio voltage pull up 1.5m sleep mode from main processor j6 scl di vddio voltage i2c clock interface h7 sda dio vddio voltage i2c data interface a1 clk32k_in di vddio voltage pull down 1.5m 32 khz clock input step down dc/dc converters & voltage regulators a4, b4 vbat_vsdc2 vdda vsdc2 step down dc/dc input power supply converter a2, b3 gnd_vsdc2 vssa vsdc2 step down dc/dc ground converter obsolete product(s) - obsolete product(s)
stw4510 ball information 9/57 a3, c4 vlx_vsdc2 aio (vbat) vsdc2 step down dc/dc output converter a5 vsdc2 ao (vbat) vsdc2 step down dc/dc output converter d9, d10 vbat_vsdc1 vdda vsdc1 step down dc/dc input power supply converter b10, c9 gnd_vsdc1 vssa vsdc1 step down dc/dc ground converter c10, d8 vlx_vsdc1 aio (vbat) vsdc step down dc/dc output converter a10 vsdc1 ao (vbat) vsdc1 step down dc/dc output converter c7 vbat_vana1_vana3 vdda vana1 & vana3 low drop input supply regulator a8 vana3 ao (vbat) vana3 low drop output supply regulator b7 gnd_vana1_vana3 vssa vana1 & vana3 low drop ground regulator b6 vbat_vdig vdda vdig low drop input supply regulator a6 vdig ao (vbat) vdig low drop output supply regulator c5 gnd_vdig vssa vdig low drop ground regulator a7 vana1 ao (vbat) vana1 low drop output supply regulator f9 vbat_vana2 vdda vana2 low drop input supply regulator f10 vana2 ao (vbat) vana2 low drop output supply regulator e9, f8 gnd_vana2 vssa vana2 low drop ground regulator j4 vbat_vmmc vdda vmmc low drop input supply regulator k5 vmmc ao (vbat) vmmc low drop output supply regulator step down dc/dc converters & voltage selection k7 vsdc1_sel0 di (vbat) vsdc1 voltage selection e8 vsdc1_sel1 di (vbat) vsdc1 voltage selection j8 vana3_sel0 di (vbat) vana3 voltage selection h8 vana3_sel1 di (vbat) vana3 voltage selection j5 vdig_sel0 di (vbat) vdig voltage selection h9 vdig_sel1 di (vbat) vdig voltage selection k6 vana1_sel0 di (vbat) vana1 voltage selection g9 vana1_sel1 di (vbat) vana1 voltage selection j7 vana2_sel0 di (vbat) vana2 voltage selection k8 vana2_sel1 di (vbat) vana2 voltage selection table 3. stw4510 ball description for the 6 mm x 6 mm package (continued) ball ball name ball type description obsolete product(s) - obsolete product(s)
ball information stw4510 10/57 2.3.2 signal description for the tfbga49 4 mm x 4 mm package interface balls k3, g3, k2, k9 h4, g2, h5 h1, k1, h3, j1, h2, f3, g1, f2, e1, e2, e3, f1 not connected ball to be left not connected other balls c1, d2, b9, d3 reserved g to be connected to ground b1, b2, b8, c2, e10, h10, j10, k10 reserved o to be left opened table 3. stw4510 ball description for the 6 mm x 6 mm package (continued) ball ball name ball type description table 4. stw4510 ball description for the 4 mm x 4 mm package ball ball name ball type description general supply balls e1 vbat_dig vddd battery supply for digital/oscillator d1 gnd_dig vssd internal ground oscillator b5 vbat_ana vdda analog part battery supply a4 gnd_ana vssa analog ground d4 vref-18 ao internal reference g6 vddio vddd io digital supply f7, g7 vminus vssd io ground digital control balls c5 pon di (nmos) pull down 1.5m power-on and reset f2 sw_resetn di (vddio voltage) pull up 1.5m software reset, reset all application, when sw-resetn =0 e3 vddok do (vddio voltage) supply monitoring for processor. interruption for high temperature warning f1 res_pro do (vddio voltage) reset for processor obsolete product(s) - obsolete product(s)
stw4510 ball information 11/57 f3 pwren di (vddio voltage) pull up 1.5m sleep mode from main processor g3 scl di (vddio voltage) i2c clock interface f4 sda di (vddio voltage) i2c data interface c3 clk32k_in di (vddio voltage) pull up 1.5m 32khz clock input step down dc/dc conversers & voltage regulators a3, b3 vbat_vscd2 vdda vsdc2 step down dc/dc input power supply converter a1, b1 gnd_vsdc2 vssa vsdc2 step down dc/dc ground converter a2, b2 vlx_vsd2 aio (vbat) vsdc2 step down dc/dc output converter b4 vsdc2 ao (vbat) vsdc2 step down dc/dc feedback converter e6, e7 vbat_vscd1 vdda vsdc1 step down dc/dc input power supply converter c6, c7 gnd_vsdc1 vssa vsdc1 step down dc/dc ground converter d6, d7 vlx_vsd1 aio (vbat) vsdc1 step down dc/dc output converter d5 vsdc1 ao (vbat) vsdc1 step down dc/dc feedback converter a7 vbat_vana1_vana3 vdda vana1 & vana3 low drop input supply regulator b7 vana3 ao (vbat) vana3 low drop output supply regulator a5 vdig ao (vbat) vdig low drop output supply regulator a6 vbat_vdig vdda vdig low drop input supply regulator b6 vana1 ao (vbat) vana1 low drop output supply regulator g5 vbat_vana2 vdda vana2 low drop input supply regulator g4 vana2 ao (vbat) vana2 low drop output supply regulator g1 vbat-vmmc vdda vmmc low drop input supply regulator g2 vmmc ao (vbat) vmmc low drop output supply regulator voltage selection e4 vana1_sel<0> di (vbat) vana1 voltage selection f5 vana2_sel<0> di (vbat) vana2 voltage selection f6 vana3_sel<0> di (vbat) vana3 voltage selection other balls (connected to ground) c1 reserved connected to ground e2 reserved connected to ground e5 reserved connected to ground table 4. stw4510 ball description for the 4 mm x 4 mm package (continued) ball ball name ball type description obsolete product(s) - obsolete product(s)
ball information stw4510 12/57 other balls (left opened) c2 reserved left open d2 reserved left open d3 reserved left open c4 reserved left open table 4. stw4510 ball description for the 4 mm x 4 mm package (continued) ball ball name ball type description obsolete product(s) - obsolete product(s)
stw4510 functional description 13/57 3 functional description 3.1 introduction the stw4510 integrates supplies for the processor cores and associated peripherals two step down dc/dc converters ? vsdc1 (programmable start-up and 1.2v default value), programmable via i2c interface, for the processor cores ( ta b l e 1 8 ) ? vsdc2, 1.8 v, for the input/output supply of all the system devices and for all peripherals which require 1.8 v supply ( ta b l e 1 9 ) five low drop regulators for general purposes. ? four of them, vana(i) (i=1 to 3) and vdig can be used for critical features like pll or analog and digital processor peripherals. these low-drop regulator output voltage values are programmable through vdig_sel [n] and vana(i)_sel[j] pads connected to vbat or to ground. ta b l e 5 shows the available output voltages. the electrical characteristics are listed in ta bl e 2 0 , ta b l e 2 1 and ta b l e 2 2 . ? the last one is vmmc and can supply different feature and in particular sd/mmc card. this regulator is completely controlled via the i2c interface. ta b l e 6 shows the available output voltages. the electrical characteristics are indicated in ta b l e 2 1 . table 5. low drop regulator output voltage programmable values ldo i (ma) output voltage values (v) 1.0 1.2 1.5 1.8 2.5 2.8 3.0 3.3 vdig 250 x (1) (100ma) 1. x means available output voltage value. xx vana1 150 x x x x vana2 150 x x x x vana3 150 x x x x table 6. vmmc low drop regulator output voltage ldo i (ma) output voltage values (v) 1.8 2.5 2.85 3.0 vmmc 150 x (1) 1. x means available output voltage value. xx x obsolete product(s) - obsolete product(s)
functional description stw4510 14/57 3.2 digital control module this module describes the interfaces used to program the device and the related registers. 3.2.1 state machine each state is described here below and represented in figure 2 off: in this mode the stw4510 is switched off. off is when pon signal = ?0?, when battery level is below 2.4v or when thermal shutdown is activated (in this particular case: not a permanent state). there is no power supply. the only active cell is the vbat level detection. osc_start: oscillator is enabled and the power up module is waiting for the rising edge of the internal signal ?osc_ok? to start power up sequence. this state duration is 300 s. start_bias: bias, reference and thermal shut-down are enabled, a counter is activated to wait for rising edge of internal signals ?pdn_regulators?. this state duration has a typical value of 7.8 ms and a worst case value of 9.46 ms. start_pm: soft start period, during this state, vdig, vsdc2 progressively reach their final values. at the end of this state, processor power supplies (vdig, vsdc2) are available, internal signal ?pdn_ls? is set to 1 and then the device can allow i2c communication, output power supply monitoring and application. typical duration of this state is 0.67ms and never goes over than the maximum duration of 1 ms. off2: stw4510 is waiting for the 32 khz processor signal. this state has an indeterminate duration. (if 32 khz is present during the states describes above, it has no effect on stw4510 behavior, 32 khz signal is taking in account by stw4510 at the end of start_pm state, the duration of this state is 0.4 ms minimum). reset: stw4510 forces a reset during 36*1/32 khz period (duration of 1.13ms) before setting res_pro signal high. this signal res_pro is high if pon is high and 32khz clock available. sleep & vsdc1_off: sleep mode ( section 3.2.3 ) and vsdc1_off mode ( section 3.2.4 ) are required by processor by setting pwren signal at low level. then vddok signal is forced to ?0?, step down dc/dc converter vsdc2, and ldo vana_i (i = 1 to 3) switch to sleep mode, smps converter vsdc1 switches off and wait for pwren signal at high level ( figure 3 ). wake-up: from sleep mode and vsdc1_off, the processor requests to switch back to high power mode (hpm) and on mode for vsdc1 by setting pwren to high level. thus the device switches regulators from low power mode (sleep) to high power mode and informs processor with vddok signal at high level ( figure 3 ). note: sleep mode has no effect on vdig nor vmmc. obsolete product(s) - obsolete product(s)
stw4510 functional description 15/57 figure 2. state machine: start-up timing vsdc2, vdig are started with internal pdn_regulators signals. i2c is available after internal ?pdn_ls? signal is set to ?1?. processor reset done on the res_pro signal is synchronous of the 32 khz clock. during power-up, pwren is masked. nevertheless, vsdc1 power supply that is controlled by pwren , is in off state during the starting phase and this up to internal signal ? pdn_ls =1? and then, the control of the vsdc1 is done via the external pwren signal. the soft start feature limits the peak current sink in the vbat supply when a supply is set to on state. 0 pon vb a t intern a l_o s c otp initi a liz a tion o s c- s t a rt 3 00 us s t a rt_ b i a i s ( 9 .5m s m a x.) b a ttery volt a ge a v a l a i b le pdn_reg u l a tor ( int. s ign a l) s t a rt_pm (1m s m a x.) vddok clock 3 2k_in off2 (0.4m s ) re s et 1.1 3 m s proce ss or re s et done => a ctive s t a te re s _pro pwren = 1 => f u ll power su pply a v a il ab le pwren = 0 => off or s leep mode a v a il ab le i2c of pmic a v a il ab le pwren 12. 33 m s m a x. vdig @ 1.2v v s dc1 @ 1.2v controlled b y pwren v s dc2 @ 1. 8 v v a n a [i] & vmmc controlled b y i2c vo u tp u t s s tw4510 1m s m a x. pwren intern a lly m as ked 1m s m a x. intern a l s ign a l pdn_l s pm00126 pon i s needed to s t a rt every s mp s a nd ldo on proce ss or in re s et mode pwren controlled b y proce ss or obsolete product(s) - obsolete product(s)
functional description stw4510 16/57 figure 3. switching from high power mode to sleep/vsdc1_off mode 3.2.2 power off / vddok in case of vddok falling edge (under voltage on vsdc1 , vsdc2 detected), the processor is reset ( res_pro low during 1.8 ms minimum) and started again with no time-out. (see figure 4 ) in case of vddok falling down edge (under pwren falling edge) the processor is not reset (res_pro keeps its high level) in case of pon falling edge (switch off of stw4510 from the main processor), the processor is also reset with no time-out. it is considered that clean switch off between modem and processor is done by software directly. t 0 intern a l_o s c pdn_reg u l a tor (int. s ign a l) vddok clock 3 2k_in pwren vdig @ 1.2v v s dc1 @ 1.2v v s dc2 @ 1. 8 v v a n a [i] & vmmc controlled b y i2c vo u tp u t s s tw4510 vdig @ 1.2v s till a ctive v s dc1 in off s t a te v s dc2 @ 1. 8 v in s leep mode (low c u rrent c a p ab ility) v a n a [i] in s leep mode (low c u rrent c a p ab ility) vmmc not a ffected b y s leep mode v s dc1 @ 1.2v, a v a il ab le a fter s t ab iliz a tion time vdig @ 1.2v s till a ctive v s dc2 @ 1. 8 v 1m s m a x s leep / off controlled b y pwren hpm hpm pm0012 8 obsolete product(s) - obsolete product(s)
stw4510 functional description 17/57 figure 4. vddok block diagram 3.2.3 sleep mode stw4510 sleep mode is only active with the presence of the 32khz clock on pin clk32_in and stw4510 power supplies vsdc2, vana1, vana2, vana3 go into sleep. the voltage is still present on the power supply output with current capability reduced. sleep mode is activated each time the pwren signal is at low level (logical 0). to exit sleep mode state it is mandatory to have the pwren signal at high level (logical 1). in this present version, sleep mode is available each time pwren = 0. when pwren = 0, some application may require that vsdc2 and/or vana(i) remain in high power mode. stw4510 may be able to comply with this requirement. for more information please contact the stmicroelectronics sales office. 3.2.4 vsdc1_off mode vsdc1_off mode is only referenced to the pwren signal. when pwren signal is high (logical level 1) the vsdc1 dc/dc regulator is in high power mode and the application processor can be supplied. in the case of pwren is low level (logical 0) vsdc1 is switched off and the consumption is reduced to the leakage current. 3.2.5 power supplies at start-up after pon, and considering the state machine, different regulators (vana(i), vdig) can be switched on or off at start-up with the default output voltage configured by the selection pin available. 9vgfbprqlwru 9vgfbprqlwru 9gg2. 67z xv n+] 9gg2. 5hvbsur w 8qghuyrowdjhghwhfwlrq 2shudwlqjyrowdjhwkuhvkrogydoxhuhdfkhg n+] obsolete product(s) - obsolete product(s)
functional description stw4510 18/57 in this present version, vdig is on at start-up and vana(i) are switched off. for more information, please contact stmicroelectronics sales office. 3.2.6 device reset by processor sw_resetn in the event of a reset from processor to stw4510, sw_resetn signal set to ?0?, the device resets all control registers, except registers at address 1eh, 1fh and 03h. as a consequence, after a sw_reset, vmmc is switched off, all vana(i) (i=1 to 3) and vdig are set to their start-up default value (on or off). when a low level is applied on pon signal, all registers are reset at their initial value and pon signal goes back to ?1?. 3.2.7 i2c interface the i2c interface controls power management and all programmable functions. i2c is configured as slave serial interface compatible with i2c registered trademark of phillips inc. (version 2.1). i2c interface description stw4510 i2c is a slave serial interface with a serial data line (sda) and a serial clock line (scl) scl: input clock used to shift data sda: input/output bidirectional data transfers it is composed of: on filter to reject spikes on the bus data line and preserve data integrity bidirectional data transfers up to 400kbit/s (fast-mode) via sda signal the sda signal contains the input/output control and data signals that are shifted in the device, msb first. the first bit must be high (start) followed by the device id (7 bits) and read/write bit control (1 indicates read access, a logical 0 indicates a write access). device id: device id in write mode: 5ch (01011100) device id in read mode: 5dh (01011101) stw4510 then sends an acknowledge at the end of an 8 bit transfer. the following 8-bits correspond to the register address followed by another acknowledge. the 8-bit data field is sent last and is also followed by a last acknowledge. table 7. device id b7 b6 b5 b4 b3 b2 b1 b0 adrid6 adrid5 adrid4 adrid3 adrid2 adrid1 adrid0 r/w table 8. register address b7 b6 b5 b4 b3 b2 b1 b0 regadr7 regadr6 regadr5 regadr4 regadr3 regadr2 regadr1 regadr0 obsolete product(s) - obsolete product(s)
stw4510 functional description 19/57 i2c interface modes figure 5. control interface: i2c format figure 6. control interface: i2c timing note: multi-write possibility is not available. for each data it is mandatory to send the address first. table 9. register data b7 b6 b5 b4 b3 b2 b1 b0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 device address 0 1 0 1 1 1 a 0 regn address regn data in write single byte start ack ack ack stop device address 0 1 0 1 1 1 a 0 regn address start ack ack device address 0 1 0 1 1 1 a 1 regn data out start ack no ack random addr single byte read device address 0 1 0 1 1 1 a 0 regn address start ack ack device address 0 1 0 1 1 1 a 1 start reg n data out ack no ack stop m+1 data bytes ack reg n + m data out random addr multi byte read ack stop start repeated stop t buf t hd_sta t f t low t r t high t hd_dat t su_dat start sda scl t su_sta t hd_sta t su_sto obsolete product(s) - obsolete product(s)
functional description stw4510 20/57 3.2.8 control registers control registers have the following functions: ? manage high power, sleep and power down modes. ? control the state machine switch on/off control of ldo?s can be done by i2c for vana(i) and vmmc. two commands exist to turn on/off the ldo?s, one is pdn_vxxx and the other one is en_vxxx (vxxx takes place of vana1/2/3 or vmmc); these commands have been put in different registers and the pdn_vxxx has a easier accessibility than en_vxxx that needs to program the two following registers 1f and 1e. these two commands control the same ldo?s and a logical or had been design between these bits. figure 7. ldo on/off control note: in the following tables, please set the bits noted ?not used? or ?reserved? at 0 when programming the registers. > 1 pdn_vxxx en_vxxx ldo on/off control table 10. register general information address type comment 00h, 01h, 02h reserved 03h r stw4510 version id 10h r/w application control register 1 11h r/w application control register 2 12h to 1dh test registers 1eh to 1fh r/w power control registers obsolete product(s) - obsolete product(s)
stw4510 functional description 21/57 register summary note: register 1fh must be sent on the i2c before the register 1eh (msb address must be sent first). application control register 1 address: 10h type: r/w reset: 0000_0000 description: register add. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved 00h reserved reserved 01h reserved reserved 02h reserved stw4510 version id 03h01000001 application control register 1 10h reserved pdn_ vana2 reserved application control register 2 11h pdn_ vana1 reserved monitoring_v sdc2 vsdc1 0 pdn_ vana3 sel_vmmc<1:0> pdn_ vmmc register 1514131211109 8 76543210 power control reserved reg address 2 bits reg address 3 bits data din/dout 4 bits en address 1fh 1eh 76543210 reserved pdn_vana2 reserved r/w [7:2] reserved [1] pdn_vana2 0: vana2 in power down mode (default) 1: vana2 in high power mode [0] reserved obsolete product(s) - obsolete product(s)
functional description stw4510 22/57 application control register 2 address: 11h type: r/w reset: 0000_0000 description: 76543210 pdn_vana1 reserved monitoring_vsdc2_vsdc1 0 pdn_vana3 sel_vmmc[1:0] pdn_vmmc r/w r (1) 1. these bits are reset (0) after reading w r/w r/w r/w [7] pdn_vana1 0: vana1 in power down mode (default) 1: vana1 in high power mode [6] reserved [5] monitoring_vsdc2_vsdc1 0: outputs in the good range (default) 1: outputs lower than expected on vsdc2 or vsdc1 [3] pdn_vana3 0: vana3 in power down mode (default) 1: vana3 in high power mode [2:1] sel_vmmc[1:0] 00: 1.8v selection (default) 01: 2.5v selection 10: 2.85v selection 11: 3v selection [0] pdn_vmmc 0: vmmc in power down mode 1: vmmc in high power mode obsolete product(s) - obsolete product(s)
stw4510 functional description 23/57 power control register @ 1eh address: 1eh type: r/w reset: 0000_0000 description: power control register @ 1fh address: 1fh type: r/w reset: 0000_0000 description: 76543210 reg address 3 bits data din/dout 4 bits en r/w r/w r/w [7:5] reg address 3 bits see ta b l e 1 1 ?address? column (lsb?s). default = 0 [4:1] data din/dout 4 bits see ta b l e 1 1 control register [0] en 0: read enabled (default) 1: write enabled 15141312109876543210 reserved reg address 2 bits reserved r/w [15:8] reserved [9:8] reg address 2 bits see ta b l e 1 1 ?address? column (msb?s), default = 0 [7:0] reserved obsolete product(s) - obsolete product(s)
functional description stw4510 24/57 power control register mapping power control register @ 05h address: 05h type: r/w reset: 0001_0000 description: table 11. power control register mapping address 1fh address 1eh comment reserved reg address data din/dout en 2-bit msb 3-bit lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h to 04h test purpose 05h to 08h setting power control register @ 05h to power control register @ 08h 0bh to 1e test purpose address 1fh address 1eh 1514131211109876543210 reserved 00101 vsdc1_prg[3:0] en r/w r/w [15:10] reserved [4:1] vscd1_prg[3:0] 0000: 1.00 v 0001: 1.05v 0010: 1.10v 0011: 1.15v 0100: 1.20v (default) 0101: 1.22v 0110: 1.24v 0111: 1.26v 1000: 1.28v 1001: 1.30v 1010: 1.32v 1011: 1.34v 1100: 1.36v 1101: 1.38v 1110: 1.40v 1111: 1.50v [0] en 0: read enabled (default) 1: write enabled obsolete product(s) - obsolete product(s)
stw4510 functional description 25/57 power control register @ 06h address: 06h type: r/w reset: 0000_1000 description: address 1fh address 1eh 1514131211109876543210 reserved 0 0 1 1 0 en_vana1 en_vdig reserved 1 en r/w r/w [15:10] reserved [4] en_vana1 0: vana in power down mode (default) 1: vana in high power mode [3] en_vdig 0: vdig in power down mode 1: vdig in high power mode (default) [2] reserved [0] en 0: read enabled (default) 1: write enabled obsolete product(s) - obsolete product(s)
functional description stw4510 26/57 power control register @ 07h address: 07h type: r/w reset: 0000_0000 description: address 1fh address 1eh 1514131211109876543210 reserved 0 0 1 1 1 en_vana3 reserved en r/w r/w [15:10] reserved [4] en_vana3 0: vana3 in power down mode (default) 1: vana3 enabled in high power mode [3:1] reserved [0] en 0: read enabled 1: write enabled obsolete product(s) - obsolete product(s)
stw4510 functional description 27/57 power control register @ 08h address: 08h type: r/w reset: 0000_1000 description: 3.2.9 it generation stw4510 has one interrupt signal: vddok . this signal has two functions: when vddok is high, vsdc1 and vsdc2 output voltages are within the right range when vddok is low, ? it means that step-up dc/dc output converter ( vsdc1 or vsdc2 ) are not regulated properly. the internal interrupt set to ?1? the bit 5 of the application control register 2 . this bit is reset after reading. ? it means that the signal pwren is low and sleep mode has been requested. address 1fh address 1eh 1514131211109876543210 reserved 0 1 0 0 0 reserved en_monitoring en_ vana2 re-served en r/w r/w r/w r/w [15:10] reserved [4] reserved [3] en_monitoring 0: disabled/ monitoring = off 1: enabled/vsdc1 & vsdc2 monitoring = on (default) [2] en_vana2 0: vana2 in power down mode (default) 1: vana2 enabled in high power mode [1] reserved [0] en 0: read enabled (default) 1: write enabled obsolete product(s) - obsolete product(s)
functional description stw4510 28/57 3.3 power management module stw4510 includes step-down dc/dc converters and regulators that supply the portable application. these supplies can work in different modes depending on the application needs. the nominal mode is called high power mode (hpm). the mode is selected by pwren signal according to the state of the portable processor and of stw4510. when pwren signal = ?0?, sleep mode and vsdc1_off are selected. high power mode is selected as default when pwren signal = ?1?. when the stw4510 has it pwren signal = ?0?, the vsdc2, vanai (i = 1 to 3) current output are reduced to save energy via the lower capability output current. each supply has a dedicated battery power supply and vdig that has low output voltage capabilities (1v, 1.2v, 1.5v) can be supplied by vsdc2 to minimize the regulator voltage drop, thus, reducing the power dissipation. each supply can be controlled and powered down through i2c programming, pwren or by pon signals, excepted vdig and vsdc2 . power down can be programmed by default at power up (special device configuration with dedicated start-up, see section 3.2.5: power supplies at start-up ) or during the application management ( power control register @ 06h , power control register @ 07h , power control register @ 08h ). in addition, an output current limitation prevents high current delivery in case of output short circuit. band gap, biasing and references have been performed by dedicated blocks. table 12. power supplies status power supplies pwren status i2c interface control status after pon - initial status 01 vsdc1 @ 1.2v off on value can be changed off vdig @ 1.2v (alive) no effect no effect no effect on vsdc2 @ 1.8v (alive) sleep mode hpm no effect on vana1 @ 2.8v sleep mode hpm switch on/off off vana3 @ 2.8v sleep mode hpm switch on/off off vana2 @ 3.3v sleep mode hpm switch on/off off vmmc @ 3.0v no effect no effect switch on/off and value can be changed off obsolete product(s) - obsolete product(s)
stw4510 functional description 29/57 figure 8. block diagram of biasing and references of the device 3.3.1 power supply domains ta b l e 1 3 lists the register bits and the signals that control the different stw4510 supply domains for each supply. bandgap all internal references vref_18 all internal biasing bias generator voltage reference control table 13. power supply domains supply name description supply domains hpm sleep power down vsdc1 step-down through vsdc1_prg[3:0] bits then vsdc1_sel[1:0] pads = 00 600 ma no pwren signal low (logical 0) vsdc2 step-down 1.8 v 600 ma 10 ma pon signal (low logical 0) vana1 ldo 1.5, 1.8, 2.5, 2.8 v vana1_sel[1:0] pads 150 ma 0.5 ma pdn_vana1 bit, or en_vana1 bit vana2 ldo 1.8, 2.8, 3.0, 3.3v vana2_sel[1:0] pads 150 ma pdn_vana2 bit, or en_vana2 bit vana3 ldo 1.8, 2.8, 3.0, 3.3v vana3_sel[1:0] pads 150 ma pdn_vana3 bit, or en_vana3 bit vdig ldo 1, 1.2, 1.5 v vdig_sel[1:0] pads 250 ma no en_vdig bit vmmc ldo 1.8, 2.5, 2.85, 3 v sel_vmmc[1:0] bits 150 ma no pdn_vmmc obsolete product(s) - obsolete product(s)
functional description stw4510 30/57 3.3.2 vsdc1 step-down dc/dc converter vsdc1 step down dc/dc converter is suitable to supply the core of the processor. vsdc1 generates the regulated power supply with a very high efficiency. the 15 voltage levels enable dynamic voltage suitable for any supply voltage of cmos process. the regulated output voltage levels are adjustable by the power control registers ( power control register @ 05h ) via i2c interface. the power up and down is controlled by the signal pwren . the step down dc/dc converter runs on the internal rc oscillator. main features: programmable output voltage: ? vsdc1_sel [1:0] pads is fixed to 00 (directly connected to ground) ? 15 levels from 1.0 v to 1.5 v (vsdc1_prg [3:0] bits of power control register - power control register @ 05h ) fixed voltage can also be selected with vsdc1_sel[1:0] (feature only available on the die and on the 6 mm x 6 mm package): ? 01: fixed output voltage1.5v ? 10: fixed output voltage1.3v ? 11: fixed output voltage1.4v 2 power domains: ? high power mode (hpm), 600 ma full load ? power down mode when step down dc/dc converter is switched off, no consumption. the switch on/off is controlled by the pwren signal. vddok signal indicates to the processor that vsdc1 supply is in the specified range. soft start circuitry from power off to high power mode specification guaranteed with input voltage from 2.7 v up to 5.5 v note: high voltage level changes can be performed according to the device monitoring constraints. please refer to the application note an2537 which explains how to change vcore value with high steps. obsolete product(s) - obsolete product(s)
stw4510 functional description 31/57 3.3.3 vsdc2 step down dc/dc converter the vsdc2 step down dc/dc converter is designed to supply the ios of the processor and its peripherals (memories ddr-sdram for example). vsdc2 output has a fixed 1.8v output voltage. the step down dc/dc converter runs on the internal rc oscillator. main features fixed 1.8 v output voltage three power domains: ? high power mode - 600 ma full load ? sleep mode with a 10 ma low current capability. ( table 19: vsdc2 dc/dc step- down converter ) fast switching from sleep mode (low current output capability) to high power mode. the step down dc/dc converter is in sleep mode when the portable processor controls the pwren signal to 0 indicating that the portable processor is able to switch to sleep mode. vddok signal indicates to the processor that vsdc2 supply is in the specified range. ? power down mode when step down dc/dc converter is switched off, no consumption. the on/off sequence is controlled by pon ; pon signal is set to 0 and vsdc1 is switched off. soft start circuitry from power off to high power mode specification guaranteed with input voltage from 2.7 v up to 5.5 v note: the definition of sleep mode is given in section 3.2.3 . 3.3.4 vana1 this ldo is dedicated, for example, to supply an analog part of a peripheral associated to a processor. main features programmable output voltage: vana1_sel[1:0] pads - 1.5, 1.8, 2.5, 2.8 v (to be fixed in the application by routing to vbat or ground). on the 4 mm x 4 mm package the selection of output voltage values is limited to sel[0] and the available voltage values are 2.5 v and 2.8 v. three power domains: ? high power mode, 150 ma full load ? sleep mode with a low current capability of 0.5 ma full load ( ta b l e 2 0 ) ? power down mode when regulator is switched off and there is no power consumption (pdn-vana1 bit of application control register ( application control register 2 ) or en_vana1 bit of power control register - ( power control register @ 06h ), it is recommended to use only the pdn_vana1 control bit. default setting defined by start-up device configuration specification guaranteed with battery voltages from 2.7 v up to 5.5 v (battery voltage of 3.5 v for a ldo output of 3.3v with full characteristics available). note: the definition of sleep mode is given in section 3.2.3 . obsolete product(s) - obsolete product(s)
functional description stw4510 32/57 3.3.5 vana2 this ldo is dedicated, for example, to supply an analog part of a peripheral associated to a processor. main features programmable output voltage: vana2_sel[1:0] pads 1.8 v, 2.8 v, 3.0 v, 3.3 v (to be fixed in the application by routing to vbat or ground). on the 4 mm x 4 mm package the selection of output voltage values is limited to sel[0] and the available voltage values are 3.0 v and 3.3 v? three power domains: ? high power mode, 150 ma full load ? sleep mode with a low current capability of 0.5 ma full load ( ta b l e 2 1 ) ? power down mode when regulator is switched off and there is no power consumption (pdn-vana2 bit of application control register ( application control register 1 ) or en_vana2 bit of power control register - ( power control register @ 08h ), it is recommended to use only the pdn_vana2 control bit. default setting defined by start-up device configuration specification guaranteed with battery voltages from 2.7 v up to 5.5 v (with a minimum battery voltage of 3.0 v for a ldo output of 2.8 v) note: the definition of sleep mode is given in section 3.2.3 . 3.3.6 vana3 this ldo is dedicated, for example, to supply a critical stage like a pll of a processor or an analog part of a peripheral associated to a processor main features programmable output voltage: vana3_sel[1:0] pads - 1.8 v, 2.8 v, 3.0 v, 3.3 v (to be fixed in the application by routing to vbat or ground). ground. on the 4 mm x 4 mm package the selection of output voltage values has been limited to sel[0] and the available voltage values are 3.0 v and 3.3 v. three power domains: ? high power mode, 150 ma full load ? sleep mode with a low current capability of 0.5 ma full load ( ta b l e 2 1 ) ? power down mode when regulator is switched off and there is no power consumption (pdn-vana3 bit of application control register ( application control register 1 ) or en_vana3 bit of power control register - power control register @ 07h ), it is recommended to use only the pdn_vana3 control bit. default setting defined by start-up configuration specification guaranteed with battery voltages from 2.7 v up to 5.5 v (with a minimum battery voltage of 3.5v for a ldo output of 3.3 v with the full characteristics available) note: the definition of sleep mode is given in section 3.2.3 . obsolete product(s) - obsolete product(s)
stw4510 functional description 33/57 3.3.7 vdig this ldo is dedicated, for example, to supply a alive digital part of peripherals associated to a processor. main features programmable output voltage: vdig_sel[1:0] pads - 1 v, 1.2 v, 1.5 v (to be fixed in the application by internal routing to vbat or ground) two power domains: ? high power mode, 100ma full load when 1v output voltage selected, otherwise 250 ma full load. ? power down mode when regulator is switched off and there is no power consumption. switch on and off is controlled by pon signal. pon is set to ?0? and vdig is switched off. vdig has its voltage output available once pon is set to ?1? and the start-up sequence has ended. default setting defined by start-up device configuration. positive supply could be generated by vsdc2 step down dc/dc converter. 3.3.8 vmmc power supply this block provides the power supply (1.8 v, 2.5 v, 2.85 v or 3 v) requested for multimedia cards applications. this ldo can also be used for any other feature in the application. main features programmable output voltage by i2c (1.8 v, 2.5 v, 2.85 v or 3 v) 2 power domains: ? high power mode, 150 ma full load ? power down mode when regulator is switched off via i2c and there is no power consumption. leakage is reduce to 1 a. specification guaranteed with battery voltages from 2.7 v up to 5.5 v (minimum vbat values are indicated in ta ble 23 ). 3.3.9 power s upply monitoring this block monitors the vsdc1 and vsdc2 output voltage. if vsdc1 or vsdc2 drop below the threshold the processor is reset. this feature can be desactivated by setting en_monitoring bit of power control register ( power control register @ 08h ) to ?0?. obsolete product(s) - obsolete product(s)
functional description stw4510 34/57 3.3.10 thermal shut-down a thermal sensor is used to monitor die temperature. as soon as the die temperature exceeds the thermal threshold, the supplies are turned off via an internal ?thermal_id? signal. the ic turns the default supply back on after around 10 ms. only the voltages present at start-up are switched on again and the device temperature can decrease. the device is ready to be controlled by i2c to supply the application again. table 14. thermal shutdown threshold description min typ max unit threshold 150 c obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 35/57 4 electrical and timing characteristics otherwise specified typical parameters are defined for ambient t = 25 c, vbat = 3.6 v. 4.1 absolute maximum ratings table 15. stw4510 absolute maximum ratings symbol description min. typ. max. units maximum power supply -0.5 7 v ta maximum operating ambient temperature -30 85 c tj maximum junction temperature -30 150 c recommended operating junction temperature 125 c vesd esd - hbm model (1) - 2 (2) 2kv vesd esd - cdm model (3) - 300 500 v 1. human body model: standard jedec: jesd22-a114d 2. except for the configuration when es d is measured versus vbat-dig -1.8kv 3. charged device model: standard jedec: jesd22-c101c obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 36/57 4.2 power supply note: stw4510 sleep mode is only active with the presence of the 32 khz clock on pin clk32_in and stw4510 has different ways to go in sleep mode. in all the following tables: high power mode is defined as ?sleep = ?0??, ?sleep mode? is defined as ?sleep = ?1? 4.2.1 operating conditions 4.2.2 vref18 table 16. operating conditions symbol description test conditions min. typ. max. units v bat power supply 2.7 5.5 v i qsleep quiescent current sleep mode 170 250 a i qstdby off mode (t = 25c) 5 a table 17. vref18 symbol description test conditions min. typ. max. units v bat supply voltage 2.7 5.5 v v ref_18 output voltage 1.78 1.8 1.84 v psrr power supply rejection ratio f 100 khz 60 db noise 100hz f 100 khz 30 v t s settling time (1) 7.8 10 ms 1. delay until pon rises at high level and 1.8 v is available on vref18 pin. obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 37/57 4.2.3 vsdc1 dc/dc step-down converter table 18. vsdc1 dc/dc step-down converter symbol description test conditions min. typ. max. units vsdc1 regulator in high power mode v bat input power supply 2.7 3.6 5.5 v v out programmable output voltage vsdc1_sel[1:0] = 00 * vsdc1_prg[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 (default) 0011 0010 0001 0000 -5% -5% -5% 1.50 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.15 1.10 1.05 1.00 +5% +5% + 5% v v ripple output voltage ripple vsdc1 = 1.2 v i out = 200 ma 10 mvpp i out output current 600 ma p eff power efficiency vsdc1 = 1.2 v i out = 200 ma 86 % i short (1) short circuit current limitation 0.9 1.2 1.4 a i (2) q quiescent current i out = 0 ma 5 a i lkg power-down current en_vsdc1 = 0 1.5 a psrr (1) power supply rejection vsdc1 = 1.2 v i out = 200 ma vpp = 0.3 v, f: [0; 20] khz 40 db s r rising slope i out = 10 ma 0.55 ms/v lir line regulation v bat : [2.7; 5.5] v 10 mv ldr load regulation i out : [0.1; 600] ma 10 mv obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 38/57 4.2.4 vsdc2 dc/dc step-down converter lirt transient line regulation vsdc1 = 1.2 v i out = 200 ma v bat = 300 mv t r = t f = 10 s 7mv ldrt transient load regulation vsdc1 = 1.2 v i out : [1; 400] ma t r = t f = 100ns 70 mv 1. guaranteed by design 2. quiescent current defined is the current measur ed on the power supply dedicated to the voltage vsdc1 table 18. vsdc1 dc/dc step-down converter (continued) symbol description test conditions min. typ. max. units table 19. vsdc2 dc/dc step-down converter symbol description test conditions min. typ. max. units vsdc2 regulator in high power mode (sleep = ?0?) v bat input power supply 2.7 3.6 5.5 v v out output voltage (1) -3% 1.8 +3% v v ripple output ripple i out = 200 ma 10 mvpp i out output current 600 ma p eff power efficiency i out = 200 ma 90 % i short (2) short circuit current limitation 0.9 1.2 1.4 a i q (3) quiescent current i out = 0 ma 5 a i lkg power-down current en_vsdc2 = 0 1.5 a psrr (2) power supply rejection i out = 200 ma vpp = 0.3 v, f: [0; 20] khz 40 db t r rising time (10 % to 90 %) 1ms lir line regulation v bat : [2.7; 5.5] v 10 mv ldr load regulation i out : [0.1; 600] ma 10 mv lirt transient line regulation i out = 200 ma v bat = 300 mv t r = t f = 10 s 7mv ldrt transient load regulation i out = [1; 400] ma t r = t f = 100 ns 70 mv obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 39/57 vsdc2 regulator in sleep mode (sleep=?1?) v bat input power supply 2.7 3.6 5.5 v v out output voltage (1) -3 % 1.8 +3 % v v ripple output ripple i out = 5 ma 10 mv i out output current 10 ma p eff power efficiency i out = 5 ma 90 % i (3) q quiescent current i out = 0 ma 2 a lir line regulation [v bat [2.7; 5.5] v 10 mv ldr load regulation i out : [0.1; 10] ma 10 mv lirt transient line regulation i out = 5 ma v bat = 300 mv t r = t f = 10 s 2mv 1. including output voltage temperature coefficient, dc line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching. 2. guaranteed by design 3. quiescent current defined is the current measur ed on the power supply dedicated to the voltage vsdc2 table 19. vsdc2 dc/dc step-down converter (continued) symbol description test conditions min. typ. max. units obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 40/57 4.2.5 ldo regulators vana1 and vana3 low drop regulators have the same characteristics, the parameters given in ta b l e 2 0 are applicable to both regulators, in ta b l e 2 0 , vana(i) stands for vana3 with the new design to reach 3.3v maximum voltage output. vana1 table 20. ldo regulators - vana 1 symbol description test conditions min. typ. max. units vana(i) regulator in high power mode (pdn_vana1 = 1, sleep = ?0?) v bat input power supply vana1 = 1.5 v/1.8 v/ 2.5 v 2.7 3.6 5.5 v vana1 = 2.8 v 3 3.6 5.5 v out output voltage vana1_sel[1:0]pads 00 01 10 11 -3 % 1.5 1.8 2.5 2.8 +3 % v i out output current 150 ma i short (1) short-circuit limitation 230 340 550 ma i q (2) quiescent current i out = 0 ma 30 a i lkg power-down current 1 a psrr (1) power supply rejection vana1 = 2.8 v i out = 150 ma vpp = 0.3 v, f: [0; 20] khz 50 db vana1 = 2.8 v i out = 10 ma vpp = 0.3 v, f: [0; 10] khz f: [10; 100] khz 50 45 db t r rising time (10 % to 90 %) vana1 = 2.8 v i out = 10 ma 1.5 ms lir line regulation v bat : [2.7; 5.5] v 5 mv ldr load regulation i out = [0.1; 150] ma 10 mv lirt transient line regulation vana1 = 2.8 v i out = 150 ma v bat = [3.0; 3.3] v t r = t f = 10 s 2mv ldrt transient load regulation vana1 = 2.8 v i out = [1; 150] ma t r = t f = 1 s 20 mv obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 41/57 vana(i) regulator in sleep mode (pdn_vana1 = 1, sleep =?1?) v bat input power supply vana1 = 1.5 v/1.8 v/2.5 v 2.7 3.6 5.5 v vana1 = 2.8 v 3 3.6 5.5 v out output voltage vana1_sel[1:0] pads 00 01 10 11 -3 % 1.5 1.8 2.5 2.8 +3 % v i out output current 500 a i (2) q quiescent current i out = 0 ma 26 a psrr ((1) power supply rejection vana1 = 2.8 v i out = 0.5 ma vpp = 0.3 v, f: [0; 20] khz 40 db lir line regulation v bat : [2.7; 5.5] v 5 mv ldr load regulation i out : [0.1; 0.5] ma 10 mv lirt transient line regulation vana1 = 2.8 v i out = 0.5 ma v bat :[3; 3.3] v t r = t f = 10 s 2mv ldrt transient load regulation vana1 = 2.8 v i out = [0.1; 0.5] ma t r = t f = 1 s 20 mv 1. guaranteed by design 2. quiescent current defined is the cu rrent measured on the power supply volt age dedicated to the vana(i) with only one vana(i) on at the same time table 20. ldo regulators - vana 1 symbol description test conditions min. typ. max. units obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 42/57 vana(i) (vana(i) with i = 2 or 3) table 21. ldo regulator - vana(i) with i=2 or 3 symbol description test conditions min. typ. max. units vana3 regulator in high power mode (en_vana3 = 1, sleep = ?0?) v bat input power supply vana(i) = 1.8 v, 2.8 v, 3 v, 3.3 v max (vana(i)_out + 0.2, vbat_min) 3.6 5.5 v v out output voltage vana(i)_sel[1:0]pads 00 01 10 11 -3 % 1.8 2.8 3.0 3.3 +3 % v i out (1) output current 150 ma i short (1) short-circuit limitation 230 340 550 ma i q (2) quiescent current i out = 0 ma 30 a i lkg power-down current 1 a psrr (1) power supply rejection vana(i) = 2.8 v i out = 150 ma vpp = 0.3 v, f: [0; 20] khz 50 db vana(i) = 2.8 v i out = 10 ma vpp = 0.3 v, f: [0; 10] khz f: [10; 100] khz 50 45 db t r rising time vana(i) = 2.8 v i out = 10 ma 1.5 ms lir line regulation v bat : [2.7; 5.5] v 5 mv ldr load regulation i out = [0.1; 150] ma 10 mv lirt transient line regulation vana(i) = 2.8 v i out = 150 ma v bat = [3.0; 3.3] v t r = t f = 10 s 2mv ldrt transient load regulation vana(i) = 2.8 v i out = [1; 150] ma t r = t f = 1 s 20 mv obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 43/57 vana(i) regulator in sleep mode (en_vana3 = 1, sleep =?1?) v bat input power supply vana(i) = 1.8 v, 2.8 v, 3.0 v, 3.3 v max (vana(i)_out+0. 2, vbat_min) 3.6 5.5 v v out output voltage vana(i)_sel[1:0] pads 00 01 10 11 -3 % 1.8 2.8 3.0 3.3 +3 % v i out output current 500 a i (1) q quiescent current i out = 0 ma 26 a psrr (1) power supply rejection vana(i) = 2.8 v i out = 5 ma vpp = 0.3 v, f: [0; 20] khz 40 db lir line regulation v bat : [2.7; 5.5] v 5 mv ldr load regulation i out : [0.1; 0.5] ma 10 mv lirt transient line regulation vana(i) = 2.8 v i out = 0.5 ma v bat :[3; 3.3] v t r = t f = 10 s 2mv ldrt transient load regulation vana(i) = 2.8 v i out = [0.1; 0.5] ma t r = t f = 1 s 20 mv 1. guaranteed by design 2. quiescent current defined is the cu rrent measured on the power supply volt age dedicated to the vana(i) with only one vana(i) on at the same time table 21. ldo regulator - vana(i) with i=2 or 3 (continued) symbol description test conditions min. typ. max. units obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 44/57 vdig table 22. ldo regulator - vdig symbol description test conditions min. typ. max. units vdig regulator in high power mode (pdn_vdig = 1); otherwise specified vin = vsdc2 (1.8 v) v in vsdc2 input power supply vdig = 1 v/1.2 v -3% 1.8 +3% v v bat input power supply vdig = 1.5 v 2.7 3.6 5.5 v v out output voltage vdig_sel[1:0] pads 00 01 10 -3 % 1.0 1.2 1.5 +3 % v i out (1) output current vdig: 1 v 100 ma vdig: 1.2 v/1.5 v 250 ma i short (1) short-circuit limitation 330 800 ma i q (2) quiescent current i out = 0 ma 43 a i lkg power-down current 1.5 a t r rising time (10 % to 90 %) vdig = 1.2 v i out = 10 ma 0.7 ms lir line regulation v bat : [2.7; 5.5] v 10 mv ldr load regulation i out : [0.1; 250] ma 10 mv lirt transient line regulation vdig = 1.2 v i out = 150 ma v bat = 300 mv t r = t f = 10 s 1mv ldrt transient load regulation vdig = 1.2 v i out = [1; 250] ma t r = t f = 1 s 40 mv 1. guaranteed by design 2. quiescent current defined is the current measur ed on the power supply voltage dedicated to the vdig obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 45/57 vmmc table 23. ldo regulator - vmmc symbol description test conditions min. typ. max. units vmmc regulator specifications (pdn_vmmc = 1) v bat input voltage v out = 3 v v out = 2.85 v v out = 2.5 v v out = 1.8 v 3.25 3.1 2.75 2.7 3.6 5.5 v v out output voltage -3% 3 2.85 2.5 1.8 +3% v i out (1) output current 150 ma i short (1) short circuit current limitation 240 360 600 ma i q (2) quiescent current i out = 0 ma 26 a i lkg power-down current 1 a psrr power supply rejection i out = 150 ma vpp = 0.3 v f < 20 khz 40 db l ir line regulation v bat : [3.1; 5.5]v 10 mv l dr load regulation i out = [1; 150] ma 10 mv l irt transient line regulation v out =2.85 v v bat : 3.1 to 3.4v t r = t f = 10 s. 2mv l drt transient load regulation i out = [1; 150] ma t r = t f = 1 s 25 mv t s settling time off->on i out = 0 ma 100 s t d discharge time on>off i out = 0 ma 1 ms 1. guaranteed by design 2. quiescent current defined is the current measur ed on the power supply voltage dedicated to the vmmc obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 46/57 4.2.6 power s upply monitoring this block monitors the vsdc1 and vsdc2 output voltage. if vsdc1 or vsdc2 drops below the threshold, the processor is reset. 4.3 digital specifications all electrical specifications having the vddio voltage as reference will be able to sustain 1.8 v or 2.8 v 5 % for vddio voltage supply. vddio ball could be connected to vsdc2 at 1.8 v or to external voltage at 1.8 v or at a maximum voltage of 2.8 v 5 % 4.3.1 cmos input/output static characteristics: i2c interface table 24. power supply monitoring symbol description test conditions min. typ. max. units threshold t hcore threshold vsdc1 vsdc1 = 1.2 v or 1.5 v -3% vsdc1-150 +3% mv vsdc1 = 1 v -3% vsdc1-100 +3% mv t hvio threshold vsdc2 -3% 1.65 +3% v table 25. cmos input/output static characteristics: i2c interface symbol description test conditions min. typ. max. units i2c interface v il low level input voltage 0.3*vddio v v ih high level input voltage 0.7*vddio v i il low level input current -1.0 1.0 a i ih high level input current -1.0 1.0 a v ol low level output voltage iol = 3ma (with open drain or open collector) 0.2*vddio v oh high level output voltage iol = 3ma (with open drain or open collector) 0.8*vddio obsolete product(s) - obsolete product(s)
stw4510 electrical and timing characteristics 47/57 4.3.2 cmos input/output dynamic characteristics: i2c interface 4.3.3 cmos input/output static characteristics: vddio level table 26. cmos input/output dynamic characteristics: i2c interface symbol description min. typ. max. units i2c interface ( figure 5 ) fscl clock frequency 400 khz thigh clock pulse width high 600 ns tlow clock pulse width low 1300 ns tr sda, scl, usbsda, usbscl rise time 20+0.1cb (1) 300 ns tf sda, scl, usbsda, usbscl fall time 20+0.1cb (1) 300 ns thd_sta start condition hold time 600 ns tsu_sta start condition set up time 600 ns thd_dat data input hold time 0 ns tsu_dat data input set up time 100 ns tsu_sto stop condition set up time 600 ns tbuf bus free time 1300 ns cb capacitive load for each bus line 400 pf 1. cb = total capacitance of one bus line in pf. table 27. vddio level: control i/os symbol description test conditions min. typ. max. units sw_resetn, vddok, res_pro, pwren, clk32k_in v il low level input voltage 0.3*vddio v v ih high level input voltage 0.7*vddio v i il low level input current -1.0 1.5 a i ih high level input current -1.0 1.5 a c in input capacitance 10 pf v ol low level output voltage i ol = tbd 0.2*vddio v v oh high level output voltage i oh = tbd 0.8*vddio v output fall time capacitance 10pf 1 ns output rise time capacitance 10pf 1 ns c i/o driving capability 100 pf obsolete product(s) - obsolete product(s)
electrical and timing characteristics stw4510 48/57 4.3.4 cmos input static characteristics: vbat level 4.3.5 nmos input: pon table 28. cmos input static characteristics: vbat level symbol description test conditions min. typ. max. units vana1_sel[0:1], vana2_sel[0:1], vana3_sel[0:1], vdig_sel[0:1], vsdc1_sel[0:1] v il low level input voltage 0.3*vbat v v ih high level input voltage 0.7*vbat v i il low level input current -1.0 1.5 a i ih high level input current -1.0 1.5 a c in input capacitance 10 pf table 29. pon input static characteristics symbol description test conditions min. typ. max. units pon v il low level input voltage 0.5 v v ih high level input voltage 1 vbat v i il low level input current -1.0 1.5 a i ih high level input current -1.0 1.5 a obsolete product(s) - obsolete product(s)
stw4510 test disclaimer 49/57 5 test disclaimer 5.1 guaranteed by design these parameters are measured during stmicroelectronics internal qualification (voltage range, temperature, etc....) which includes full characterization on standard and corner batches of the process. these parameters are partially measured or not measured at all during production testing. 5.2 fully tested on package only these parameters are measured during stmicroelectronics internal qualification (voltage range, temperature, etc....) which includes full characterization on standard and corner batches of the process. these parameters are fully tested on package only and partial tests are performed on wafers. obsolete product(s) - obsolete product(s)
application information stw4510 50/57 6 application information 6.1 components list table 30. components list name value comments function c1 10f in the complete system application, the sum of the capacitors connected on each stw4510 ball must never be less than 30% of the value indicated in the typical value column of this table. this includes all capacitor parameters: ? production dispersion ? dc bias voltage applied ? temperature range of the complete system application ? aging vbat_vsdc1 decoupling c6 vbat_vsdc2 decoupling c9 vbat_ana decoupling c2 22f vsdc1 output filter c7 vsdc2 output filter c4 1 f vbat_osc output filter c5 vddio output filter c11 vbat_dig output filter c13 vbat_vana1_vana3 output filter c16 vbat_vana2 output filter c18 vbat_vmmc output filter c10 2.2f vref output filter c12 vdig output filter c14 vana3 output filter c15 vana1output filter c17 vana2 output filter c19 vmmc output filter l1 4.7h see: table 31 coil vsdc2 dc/dc l2 coil vsdc1 dc/dc table 31. list of 4.7 h coils supplier part number dcr ( )irms (1) (a) l x l x h (mm x mm x mm) tdk vlf3010at-4r7mr70 0.28 0.7 2.8 * 2.6 * 1.0 vlf3012at-4r7mr74 0.16 0.74 2.8 * 2.6 * 1.2 vlf4012at-4r7m1r1 0.14 1.1 3.7 * 3.5 * 1.2 mlp2520s4r7l 0.11 1.1 2.5 * 2 * 0.85 murata lqh2mc-2 series 0.46 0.5 2.0 * 1.6 * 0.9 lqm31p_n4r7m00 0.3 0.7 3.2 * 1.6 * 0.85 lqm2hp_go series 0.11 1.1 2.5 * 2 * 0.9 1. irms: 30% decrease of initial value obsolete product(s) - obsolete product(s)
stw4510 application information 51/57 6.2 application schematics figure 9. stw4510 application schematics vbat_vsdc2 vsdc2 vlx_vsdc2 gnd_vsdc2 vbat_vsdc1 vsdc1 vlx_vsdc1 gnd_vsdc1 vbat_ana gnd_ana vref_18 vbat_vdig gnd_vdig vdig vbat_vana1_vana3 gnd_vana1_vana3 vana1 vbat_vana2 gnd_vana2 vana2 vana3 vbat_vmmc vmmc vbat_osc gnd_osc vddio gnd_io clk32k_in pon vddok res_pro pwren sw_reset sd a scl vbat l2 c6 vsdc2 vbat c1 vsdc1 c2 l1 c7 vbat c4 c5 ( * ) v s dc2 or gener a l s y s tem vddio, depending on the complete s y s tem a rchitect u re portable processor su pply volt a ge s election 0 u tp u t ba ll s v s dc1_ s el<0> v s dc1_ s el<1> v a n a3 _ s el>0> v a n a3 _ s el<1> vdig_ s el<0> vdig_ s el<1> v a n a 1_ s el<0> v a n a 1_ s el<1> v a n a 2_ s el<0> v a n a 2_ s el<1> c9 c10 vbat vdig vbat c11 c12 c13 c14 vana3 vana2 vana1 vbat c15 c16 c17 vmmc c18 c19 stw4510 pm001 3 0 vsdc2(*) obsolete product(s) - obsolete product(s)
package mechanical data stw4510 52/57 7 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. 7.1 tfbga 84 balls 6 mm x 6 mm x 1.2 mm see figure 10: tfbga84 6 mm x 6 mm x 1.2 mm outline drawing . table 32. tfbga84 6 mm x 6 mm x 1.2 mm - 0.5mm ball pitch (1) (2) 1. these measurements conform to jedec standards 2. drawing dimensions parameter min. typ. max. unit a 1.16 mm a1 0.20 0.25 0.30 mm a2 0.82 mm b 0.25 0.30 0.35 mm d 5.90 6.00 6.10 mm d1 4.50 mm e 5.90 6.00 6.10 mm e1 4.50 mm e 0.45 0.50 0.55 mm f 0.65 0.75 0.85 mm ddd 0.08 mm obsolete product(s) - obsolete product(s)
stw4510 package mechanical data 53/57 figure 10. tfbga84 6 mm x 6 mm x 1.2 mm outline drawing note: the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. obsolete product(s) - obsolete product(s)
package mechanical data stw4510 54/57 7.2 tfbga 49 balls 4 mm x 4 mm x 1.2 mm table 33. tfbga49 4 mm x 4 mm x 1.2 mm, 0.5mm pitch reference min. typ. max. unit a 1.2 mm a1 0.15 mm a2 0.8 mm a3 0.2 mm a4 0.6 mm b 0.25 0.3 0.35 mm d 3.85 4.00 4.15 mm d1 3.00 mm e 3.85 4.00 4.15 mm e1 3.00 mm e0.50mm f0.5mm ddd 0.08 mm eee 0.15 mm fff 0.05 mm obsolete product(s) - obsolete product(s)
stw4510 package mechanical data 55/57 figure 11. tfbga49 4 mm x 4 mm x 1.2 mm outline drawing obsolete product(s) - obsolete product(s)
ordering information stw4510 56/57 8 ordering information 9 revision history table 34. order codes order codes package packing STW4510AET tfbga84 6 mm x 6 mm x 1.2 mm tape and reel stw4510ae tfbga84 6 mm x 6 mm x 1.2 mm tray stw451027t/hf tfbga49 4 mm x 4 mm x 1.2 mm tape and reel stw451027/hf tfbga49 4 mm x 4 mm x 1.2 mm tray table 35. document revision history date revision changes 21-mar-2008 1 initial release. obsolete product(s) - obsolete product(s)
stw4510 57/57 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s)

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